1. Field of the Invention
The present invention relates to a memory control device having a memory controller for controlling an operation of DRAM such as a synchronous dynamic random access memory (SDRAM) and a power controller for controlling a power supply for the memory.
2. Related Background Art
In the past, regarding electronic circuits of a computer, in a system in which an SDRAM must be battery-backed up if supplying power from exterior is interrupted, for example, upon power stoppage, the following procedures have been adopted:
(1) During the power stoppage, power is supplied from a battery to a memory controller itself so as to continue to control an interface to the SDRAM to be backed up; or
(2) If the supplying power to the memory controller itself is stopped, a control signal between the memory controller and the SDRAM is switched by a switch, and a controller other than the memory controller controls the SDRAM to be backed up. However, in the above conventional procedure (1), since the battery power is consumed by the memory controller itself, as well as the SDRAM to be backed up, there was a disadvantage that a back-up sustaining time is short. Particularly, in a case where the memory controller is incorporated into a large scale application specific integrated circuit (ASIC), since the battery power is supplied to the entire ASIC, the back-up sustaining time is further shortened.
On the other hand, in the conventional procedure (2), since the power to the memory controller is stopped, although the disadvantage encountered in the procedure (1) can be eliminated, since an additional circuit such as the switch must be provided between the memory controller and the SDRAM, delay in the control signal is caused, with the result that it is very hard to increase operating frequency of the SDRAM. Incidentally, of course, this problem is also encountered in a DRAM, as well as the SDRAM.